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Electronic Computer Aided Design (ECAD) tools have played a crucial role in electronics development since the 1970s. Early circuit simulation programs such as SPICE helped design engineers analyze and optimize their proposed circuit designs to reduce prototyping effort and improve system performance. Since that time, assortments of CAD tools have evolved into complete integrated design frameworks for Integrated Circuits (ICs), Printed Wiring Boards (PWBs), and Multichip Modules (MCMs). Many of these systems are very sophisticated, and serve the design needs for a wide variety of engineering disciplines.
The Special Purpose Processor Development Group (SPPDG) found itself in need of specialized ECAD tools to assist in the design and simulation of high performance non-silicon digital integrated circuits, and systems constructed with these specialized chips, in the early 1980s. There were few ECAD tools and NO design frameworks at that time, so it was necessary to develop the appropriate tools and supporting framework to assist in the design and implementation of high clock rate digital signal processors. The Mayo-developed tools became an integrated system called MagiCAD.
The SPPDG used MagiCAD almost exclusively for semicustom GaAs IC design from the mid-1980s until 1998. By that time, simply maintaining the complex infrastructure of an ECAD system became a significant effort. Meanwhile most of the major commercial ECAD vendors had improved their tool suites significantly, adding flexibility and support for "deep sub-micron" features which were similar to the design issues in high speed GaAs IC design. Today Mayo has many different commercial ECAD tools for semicustom IC, printed wiring board, and MCM design available in-house.
One important component of high clock rate system design is attention to the details of the electronic packaging into which the high performance integrated circuits are installed.
By the mid-1970s it was clear to the Mayo group that inductive and capacitive parasitics in the single chip packages employed for silicon ECL components, as well as the interconnect between these high performance chips, significantly reduced the performance of the overall system. This realization led to a series of IC package and prototype designs with the primary goal of fully exploiting the capabilities of the ECL chips. Early package prototyping required fabrication and testing of chip carriers to determine if the packages met the system design goals.
The Mayo SPPDG began developing electromagnetic simulation tools in 1980 to create a capability to predict the parasitic capacitances and inductances in both the chip carriers and the intervening interconnect. The development by 1985 of Multilayer Multiconductor Transmission Line (MMTL) Analysis tools created the capability of predicting, with a high degree of accuracy, the performance capabilities of inter-chip interconnect. Several versions of MMTL were created for lossy and loss-free transmission line analysis. Single chip package prototyping was then conducted in simulation, and it was possible to create new chip carrier designs using these tools (Figure S-1).
However, simply predicting parasitic capacitances and the resulting crosstalk was not sufficient to completely understand signal behavior between high speed ICs. It was necessary to develop waveform simulators that could account for all of the crosstalk, dispersion, and reflection characteristics of the interconnect: effects which are highly frequency dependent, and are not well modeled by SPICE-like time domain simulators. The Mayo team created a series of frequency domain waveform simulators that could predict all of these effects in a closed form solution (Figure S-2).
The first set of waveform simulators developed at Mayo are based on the Telegrapher's Equations, which rely on the so-called quasi-TEM assumptions. These assumptions simply imply that the electric and magnetic field components of the moving wavefront are orthogonal to the direction of wavefront propagation in the transmission line. These assumptions are considered valid whenever the signal wavelengths are significantly larger than the cross-sectional dimensions of the transmission line. To assure that we remain within the region of validity for these assumptions, we generally constrain the use of these techniques to bandwidths of 2-5 GHz, although the limitations also scale with smaller interconnect geometries.
Unfortunately, the real-world of inter-chip interconnect does not match a simple coupled transmission line model. Real interconnects have multiple sources and/or destinations, vias, traverse various metal layers on a chip, circuit board, or MCM, and exhibit a variety of discontinuities in the form of bond wires or connectors.
To accommodate these very complex interconnect structures, (Figure S-3), the Mayo SPPDG created the Networking Tool, which can simulate multiple interconnected coupled transmission line environments with an arbitrary topology and a variety of discontinuities. The Networking Tool has been successfully employed to model a number of single-chip IC packages and multiple chip system applications (Figures S-4 and S-5).
New developments in transistor technology have continued to push analog system frequencies and digital clock rates well beyond the realm of the quasi-TEM assumptions upon which the early transmission line and waveform analysis were based. As digital clock rates enter the 10-100 GHz range, it is necessary to accurately model the electromagnetic behavior of circuits from DC to (approximately) five times the system clock rate. This is accomplished by the application of full-wave algorithms which accurately model electromagnetic behavior without limitations on frequency.
Mayo has developed a full-wave transmission line simulator based on the Finite Edge Element Method (FEEM), which is derived from vector finite element methods. This tool has been shown to be about ten times faster than traditional Finite Element Method programs. This makes it possible to directly simulate all frequencies of interest, instead of relying upon numerical extrapolation techniques (Figure S-6).
The characterization of "noise" in the power distribution planes of a multichip module or printed wiring board is now becoming an area of concern to the designers of commercial electronics systems, such as microprocessors operating at 200-2000 MHz clock rates, primarily because power and ground noise can dramatically affect electronics systems operating at these rates. This topic has been an area of concern to the designers of extremely high performance digital and mixed signal military systems throughout this decade. However, until recently, very little progress has been made in its solution.
The Mayo team has been working aggressively on these problems since 1992, and we have already developed a number of efficient fast-quasi and 3D full-wave power/ground plane noise simulators for frequencies up to 100 GHz using generalized Z and S-parameters employed in microwave network analysis. These present first-generation algorithms and EM tools (Figure S-7) are being extended to higher frequencies with improved accuracy, and include measurement de-embedding, full-wave active device models, and more complex physical geometries.
As we applied the early power and ground plane noise modeling tools to a number of problems, we have come to understand that the circuit concepts underpinning traditional intuition about power and ground plane noise have been completely wrong. Furthermore, the engineering "rules of thumb" that we have developed to suppress noise in the power systems, based on intuition and trial and error, are also sometimes wrong. We have discovered, for example, that simply choosing the correct component placement on a printed wiring board can have a very dramatic effect on the amount of power and ground plane noise created in the system. We published this example of a two chip system, where clever selection of component placement suppresses the power system noise over wide ranges of frequency (Figure S-8).
Research is continuing on the fundamental properties of power and ground plane noise propagation, and we are continuing to develop new algorithms, techniques, and simulation tools to help us better understand and model power system noise.
Several new guided wave electromagnetic (EM) simulation technology areas still need to be addressed for future generations of electronics systems. A new generation of efficient full-wave algorithms and simulation tools need to be developed to characterize emerging-technology semiconductor devices and their immediate environment. New tools are needed to analyze device-to-device and device-to-interconnect coupling of entire digital standard cells (several to many transistors) while maintaining full-wave fidelity above 100 GHz. Full-wave circuit analysis will be needed to design digital and mixed signal integrated circuits. New power delivery system design tools will be required to ensure that multichip systems will function correctly at speed. In addition, a better understanding of the high frequency electrical non-linearity of present-day packaging is needed to develop future generations of electronic systems.
It should be noted that development of electromagnetic modeling tools is one of the most difficult endeavors in present day ECAD technology. Literally years of effort must be invested in the development of algorithms and mathematical techniques that will accurately model a subset of the EM problems in high speed system design. Once the algorithms have been created and tested in limited simulation programs, the ECAD tool development team must generalize the algorithm, add error handling and code to predict numerical accuracy, create the graphical and non-graphical user interfaces, and tie the simulator into the design framework for the electrical engineers. Once the new simulation tool is in place, the results of the simulations must be carefully verified as its use is extended to each new problem. EM simulators developed by the Mayo team have always been verified by fabricating and testing physical structures designed exclusively to determine the accuracy of the simulation tool. By using a closed loop of simulator development, simulation, and testing, Mayo has been able to identify and correct shortcomings in the simulation tools as we applied them first to Printed Wiring Boards (PWBs), then to Multichip Modules (MCMs), and most recently to on-chip interconnects.
The SPPDG is in the process of developing several new algorithms and software tools in cooperation with our long-term collaborator, Dr. George Pan at Arizona State University. The new algorithms and tools will focus on modeling the advanced physics and EM coupling within and between interconnect and transistors fabricated in low-bandgap antimonide based compound semiconductor processes. The simulation tools will, in part, prepare us to design electronics systems which will fully exploit devices capable of 100 GHz digital clock rates and analog center frequencies in the V- and W-bands (60 GHz and 94-110 GHz, respectively). The tools will be developed, verified, and employed in the context of advanced materials, devices, and packaging research already being conducted at Mayo. Results from the algorithm and tool development will be published and shared with the Department of Defense design community to facilitate widespread utilization of the new device technologies. New algorithms and simulators will first be published in the refereed journals, and will appear on our publications list.
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Page Modified: February 11, 2002
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