SPPDG Simulation and Analysis


Overview

The Mayo Foundation Special Purpose Processor Development Group (SPPDG) simulation and analysis capabilities are focused on effective modeling of high performance systems and technologies to ensure first pass design success and to aid in developing new integrated circuit and packaging technologies. With a significant effort involved in the development of very high speed digital systems (i.e., often exceeding 10 Gbps data rates with active research in attaining up to 100 Gbps), the SPPDG is continually analyzing new and experimental semiconductor technologies. At the same time, the SPPDG continues to exploit conventional semiconductor technologies such as full-swing complimentary metal oxide semiconductor (CMOS).

Outside the purely digital regime, the SPPDG simulates and analyzes various mixed signal and wireless systems ranging in frequency from L-Band (e.g., Global Positioning System [GPS] receiver at 1.575 GHz) to V-Band (e.g., 60 GHz digital wireless network transferring 2.5 Gbps per channel) to even yet unexploited bands such as 300 GHz to 1 THz frequencies. To ensure that the full bandwidth of the various integrated circuit (IC) technologies is realized in a systems environment, careful attention must be given to packaging technologies for both mainstream IC technologies, utilizing many signals at moderate data rates, and high performance IC technologies, which utilize only a few signals operating an ultra-high data rates.

Packaging Technology Analysis

With ever-increasing performance requirements, the need to reduce packaging parasitics becomes ever more crucial to system success. More than fifteen years ago, the SPPDG recognized this need and began investigating multi-chip module (MCM) packaging for high performance applications. With little information or test data available on the high performance aspects of the various MCM technologies, the SPPDG began a large study in the late 1980's to characterize and compare numerous MCM technologies, including laminate (MCM-L), ceramic (MCM-C), and deposited (MCM-D) processes. To provide a badly needed service to industry and government collaborators and to prevent duplicating the efforts of other researchers, the SPPDG concentrated on characterizing the high frequency performance of MCM technologies.

To aid in the study, a set of structures was developed specifically for high frequency characterization and comparison. These structures have since been fabricated in nearly two dozen MCM technologies. When possible for each technology, Mayo designed the substrates, paid for the fabrication, worked within the vendor's design rules, and fully characterized the electrical performance of the resulting structures. A vector network analyzer (e.g., HP8510 with a frequency range from 45 MHz to 26.5 GHz) and a time domain reflectometer (e.g., Tek11801 with a <35 psec risetime) were utilized when measuring these structures.

Utilizing the resulting measurement database, the SPPDG is able to compare different technologies for performance, routing density, inter-signal coupling (i.e., crosstalk), and manufacturing tolerance. In addition, the SPPDG is able to provide feedback to the substrate vendors with information on their technology's performance relative to others and methods to improve their technology.

To understand the reasons for the variations in the different technologies, the SPPDG physically makes cross sections of example substrates, polishes the substrate edges, and takes either photo-micrograph or scanning electron microscope (SEM) images of the cross sections (Figure SIM-1). Views of the vias, power planes, and transmission lines provide significant insight to the manufacturing tolerances and electrical performance of each technology. In addition, atomic force microscopy (AFM) provides detailed images of surface height variation (Figure SIM-2).



Figure SIM-1
SEM Photographs of MCM Via Structures


Figure SIM-2
AFM Measurement of MCM Surface Variation

In order for the SPPDG to gain full access to the MCM vendors' technologies, much of the MCM packaging analysis work was performed under nondisclosure agreements, and thus cannot be released in its present form to the general electronics community. Nonetheless, when possible, the SPPDG publishes papers and reports in public fora and continues to expand the study with new electronic packaging technologies as they arise.

Integrated Circuit Technology Analysis

In order to achieve the required performance goals, the SPPDG has been involved with a large variety of semiconductor technologies including conventional "bulk" silicon (Si), silicon on insulator (SOI), silicon germanium (SiGe) BiCMOS, gallium arsenide (GaAs), gallium nitride (GaN), indium phosphide (InP), quantum well resonant tunneling diode (RTD), and more recently antimonide (Sb) based devices. Each of these technologies has its respective strengths and deficiencies, and the SPPDG has analyzed each of them to provide industry and government collaborators with unbiased comparisons. Where possible, the SPPDG compares the technologies at the discrete transistor level and implementing both analog (Figure SIM-3) and digital functions (Figure SIM-4).


Figure SIM-3
Bipolar Analog Amplifier Performance


Figure SIM-4
Digital Inverter Performance

Using the results of these analyses, the SPPDG is able to support the development of emerging systems and IC technology development both within the SPPDG and for our external collaborators.

Model Development

Prior to performing any simulations, the SPPDG must first obtain or generate models of the discrete devices, integrated circuit devices and corresponding packaging. Whenever possible, the SPPDG obtains existing models and verifies them for accuracy. Nonetheless, the need to generate models arises in most efforts.

Because of the large variety of packaging technologies available, the SPPDG is forced to develop packaging models using a wide variety of techniques. For low frequency applications, lumped element models are generally adequate. When possible, the SPPDG develops lumped element packaging models with two approaches, comparing the results for validity. In a theoretical approach, a model is developed using electromagnetic (EM) simulators like those developed at Mayo, using the material properties and physical dimensions of the packaging interconnect, planes, dielectrics, etc. In an empirical approach, lumped element parasitics are measured in the SPPDG's state of the art test laboratory (Figure SIM-5). When the two approaches agree, then the resulting model is used with confidence.


Figure SIM-5
Empirical Approach to Electrical Modeling

For more complicated and higher frequency packages, which require distributed-element models, the theoretical approach described above is used to generate a suitable model (Figure SIM-6). For cases where the "as designed" material dimensions are either not available or suspect, a more involved process utilizing tools in the SPPDG cleanroom is required to develop an accurate model. In some cases, X-ray images are taken of the package to gain insight to the inner structure (Figure SIM-7). If the X-ray image is not adequate, the packages are lapped down slowly to reveal the metal pattern, layer by layer. The layer patterns and geometries are then used in conjunction with cross section images taken with a SEM (Figure SIM-8) or transmission electron microscope (TEM) to develop a complete package model using EM modeling tools.


Figure SIM-6
Theoretical Approach to Electrical Modeling


Figure SIM-7
X-Ray Image of Ceramic Package


Figure SIM-8
SEM Images of MCM Cross Sections

Whenever possible, the SPPDG validates its packaging models by comparing the simulated performance of the resultant models to measured data in the time and/or frequency domains from representative packaging (Figure SIM-9).


Figure SIM-9
Modeled vs. Measured TDR performance

The SPPDG can also generate individual transistor models from measured or simulated data (Figures SIM-10 and SIM-11). The measured data can be either be obtained from the fabricator of these devices or through measurement of these devices in the SPPDG test laboratory using commercial tools or software developed at Mayo. The commercial tools are also used to extract model parameters from both DC and high-frequency measured data. These tools are industry standard and can generate models for nearly every IC technology with which the SPPDG is involved.


Figure SIM-10
Modeled vs. Measured DC curves for an individual transistor



Figure SIM-11
Modeled vs. Measured S-parameter data for an individual transistor

Circuit and System Analysis

With the required circuit and packaging models in-hand, the SPPDG can perform a wide range of analyses using a variety of tools, the most common of which is a signal integrity simulation of critical interconnect paths. Using custom scripts and tools, as well as common simulation engines, simple to complex input waveforms can be simulated and eye diagrams can be automatically generated for complex systems (Figure SIM-12), which can then be used to aid in the proper design of the interconnect, input/output buffers (Figure SIM-13), amplifiers, etc. In addition, manufacturing tolerances can be taken into account with Monte Carlo simulations (Figure SIM-14) to ensure proper operation under a wide variety of conditions.


Figure SIM-12
Eye Diagram Simulations


Figure SIM-13
Example of Need for Custom CMOS Buffer


Figure SIM-14
Monte Carlo Simulation

For circuits with significant switching noise issues (Figure SIM-15), the power and ground delivery system, along with decoupling capitance (Figure SIM-16) and associated parasitics, must also be modeled to determine their effects on signal integrity.


Figure SIM-15
Simultaneous switching noise model of MCM

Figure SIM-16
Effects of decoupling capacitance on simultaneous switching noise

In most instances, the complexity of the analyzed system falls well within the capability of the available simulation tools. Nonetheless, there are several instances where the system being analyzed is far too complex to be effectively simulated. One common example of an effect that most often falls outside the effective capability of commercially available simulation tools is noise on ground and power planes in mixed signal systems, where it is quite common to have dozens-to-hundreds of components attached to the ground and power planes. In these cases, the SPPDG has developed a custom chamber with probes and software to measure a "noise profile" over an entire surface (Figure SIM-17). Using this tool, the SPPDG is able to determine where the ground and power plane noise is the strongest, where noise-sensitive components (e.g., low noise amplifiers) should be placed, where the noise is being generated (e.g., a microprocessor), and where decoupling capacitors should be placed to be most effective. In addition, Mayo is continually developing new algorithms to predict the same noise surfaces through simulation tools.


Figure SIM-17
Equipment for Power and Ground Plane Characterization

A growing number of electrical systems are now being integrated with optical devices. To perform a complete system analysis, the optical effects must taken into consideration while modeling the electrical effects (Figure SIM-18).


Figure SIM-18
Modeling of electrical and optical effects

Simulation and Analysis Tools Within the SPPDG

To prepare physical samples for test and characterization, the SPPDG cleanroom has several pieces of equipment at its disposal which enable rapid turnaround.

To make electrical measurements on test devices, the SPPDG test laboratory has a wide variety of commercial and custom tools.

For simulations, the SPPDG utilizes several commercial tool suites.

For more information on the SPPDG's simulation and analysis capability, feel free to contact Gregg Fokken.


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Page Modified: January 22, 2002

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