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The need for prototype, high frequency signal processors at the Mayo Clinic was originally driven by a project at Mayo in the 1970s to develop a very advanced, three dimensional, real time X-ray computed tomography (CT) scanner, referred to as the Dynamic Spatial Reconstructor (DSR).
This experimental X-ray CT scanner (Figure EP-1) generated large volumes of data which needed to be acquired and displayed very quickly to be useful. By 1975 it had become apparent that the only viable integrated circuit (IC) technology which could be used to fabricate special purpose computers capable of addressing these required high data rates was the Emitter-Coupled Logic (ECL) 100K logic family. This family of logic, packaged in both 24 pin dual inline packages (DIPs) and flat packs (FPs), operated in the 100 megahertz (MHz) to 200 MHz clock rate range for signal processor prototypes utilizing approximately 200 ICs. Of critical concern was that the ECL 100K "data book" values indicated that clock rates at least twice as high should be achievable with these ECL 100K components.
Laboratory testing at Mayo eventually revealed that the limitation in the performance of the ECL 100K chips was the packages into which they were typically installed by the chip manufacturer. To address the problem of the IC packaging limiting the performance of the ICs themselves, during 1976-78 Mayo performed evaluation studies on many different commercially available IC packages. The resistance, inductance and capacitance measurements conducted at Mayo revealed that the leads of the DIPS (and, to a somewhat lesser degree of the FPs) exhibited very high values of inductive and capacitive parasitics. Since the primary concerns of the packaging industry at that time were purely in regard to the mechanical aspects of the packages, with virtually no attention given to the electrical issues (with the possible exception of DC lead resistance), many of the packages simply could not perform well at higher frequencies. To address the high frequency AC packaging issues, in 1979 the Mayo group began the design of a family of custom leadless chip carriers (Figure EP-2), with serious attention given to their high frequency behavior. This family of chip carriers was designed to be used with both ECL 100K logic and memory components, thus requiring two different die (die refers to an unpackaged IC) cavity configurations, yet with a common input/output (I/O) pin footprint. This approach to the design of the packages in the family assured that a single package footprint could be used on the system boards to accommodate both package types.
Early Gallium Arsenide (GaAs) components designed by Mayo were targeted for this package as well. Many different versions of the package, comprising an entire family, were designed and fabricated, utilizing multiple vendors. The evolution of this package design was based almost totally on measurement results from each previous version thereof, because of, at that time, a near total lack of suitable electromagnetic CAD/simulation tools. Over a four year period (1979-1983) , the original package evolved from a minimized parasitics version to a controlled impedance version with power/ground plane construction, in-cavity and back surface power supply decoupling, and signal termination. The final complete family contained nearly thirty slightly different versions of a common chip carrier footprint, each version emphasizing a different set of strengths and limitations.
Coordinated with the 28 I/O chip carrier design was the development of high frequency prototyping printed circuit boards (PCB's) for developing high performance systems (Figure EP-3).
The early versions of these printed circuit boards contained a power and ground plane sandwich construction, varying from three to twelve power/ground layers, but no buried signal layers. All signal connections were made with twisted pair wirewrap wire (Figure EP-4), which provided a moderately controlled 75 ohm impedance transmission line environment for each signal net. In conjunction with the prototype boards, custom terminator resistor networks were developed and capacitors were characterized to determine which materials and case styles performed the best over a broad frequency range. The combination of the chip carriers, specially designed circuit boards, and specialty components resulted in wire wrapped ECL circuits that operated as high as 570 MHz clock rates and direct, point to point, wired GaAS circuits which performed at over 1 gigahertz (GHz) clock rates.
The completion of the 28 I/O package family was followed in the early 1980s by our development, for chips with higher pad counts, of four different types of 88 I/O packages (cofired alumina, cofired beryllia, single layer and metalization (SLAM) alumina, and thin film metalization on alumina), followed in the mid 1980s by a thin film 216 I/O package with 192 integral termination resistors. The ten year effort to create single chip packages for high performance integrated circuits eventually was terminated after the development of a 240 I/O elastomer mounted package of dimensions .750 inches square. Each of these packages had a companion prototyping board, with prototype components that operated in the 500 MHz to 1 GHz range.
During the development of the single-chip packages described above, it became clear that irrespective of the quality of the design of any given single-chip package, the package imposed significant electrical performance constraints on the chips because of residual parasitic inductance and capacitance, and on the circuit boards and the resulting signal processor systems because of the large amount of real estate consumed by the packages (package areas were 15-60 times the areas of the chips themselves). The solution to these electrical and mechanical problems was the complete elimination of the IC package, and a conversion to multichip packaging approaches such as hybrids and multichip modules (MCMs), which may be thought of as microminiature circuit boards, on which bare integrated circuits are installed and connected to extremely narrow traces on the surface of and buried within the MCM. In 1987 the Mayo SPPDG began investigating several potentially viable MCM technologies for use in the packaging of multiple bare chips (die) on the same microminiature circuit board (ie., MCM) substrate. Based on past experiences with cofired ceramic single chip packages, as well as with many advanced printed circuit board technologies (similar to what is now referred to as MCM-Laminate), it appeared that the MCM-Deposited (MCM-D) technology offered the most promising option for high clock rate signal processor systems. A two-step process was undertaken to evaluate the new MCM technologies. First, MCMs with passive interconnect line structures were designed and fabricated. These first experimental MCMs became known as passive test coupons, with each serving as the characterization vehicle for one of the MCM technologies. The second step was the design of active circuit demonstration modules using high performance GaAs chips. The very first MCM designed at Mayo was a combined passive/active vehicle; it was fabricated in 1988 (Figure EP-5).
The technology chosen for this first experimental coupon was a thin film, copper/polyimide, multilayer MCM-D process, which was at that time a state of the art fabrication process with five metal layers, with 1 mil line widths and the ability to support up to three 50 ohm, controlled impedance signal layers. This initial test coupon was characterized at frequencies up to 26 GHz. This coupon also contained eight bare GaAs die, with operational clock rates up to 1 GHz. This same approach was employed with many other subsequent MCM vendors and fabrication processes. A "standard passive coupon" design emerged from this work over a period of several years, so that the same structures could be implemented in each MCM technology, allowing comparisons and trade-offs to be made among the various MCM technologies. Active circuit demonstrations proved that many of these technologies could support clock rates up to 2.5 GHz.
Numerous and quite diverse MCM technologies were explored, including:
We also explored the incorporation directly into the MCM substrates of passive electrical components such as resistors, capacitors and inductors, thereby conserving the surface areas which would normally have to be committed to discrete passive components (Figure EP-7).
Other demonstrations of MCMs containing high performance integrated circuits have included a small family of sixteen chip GaAs demonstration modules, each of which utilizes sixteen, 2,000 gate GaAs configurable gate arrays; each 16-chip module had a total of 520 I/O (Figure EP-8).
This 16-chip design was used in numerous studies as an active circuit benchmark in many MCM technologies. A portion of this 16-chip design was also implemented in two different flip chip attachment technologies.
In the mid 1990s the Mayo group undertook an investigation of the high-frequency performance of laminate multichip module (MCM-L) technology, with the goal of demonstrating its appropriateness for the development of all-digital receivers operating at analog frequencies in the 4-6 GHz range, and clock rates in the 8-12 GHz range. Several test modules were developed, including a unique "paired" substrate (Figure EP-9): The upper half of the pair contained a mixed-signal circuit, while the bottom half of the pair contained all-digital chips. The mixed-signal substrate contained sites for a "mockup" of an all-digital receiver including a low noise amplifier, three separate A/D converter part types, and demultiplexers; and two low noise amplifiers, one with and one without an integrated filter. The digital substrate contained sites for a 7-chip NEL circuit, a 2-chip clock circuit, a 4:1 multiplexer, a 1:4 demultiplexer, and a 1K gallium arsenide gate array. The MCM substrates were fabricated from a cyanate ester-impregnated PTFE dielectric material. Figure EP-10 shows that the seven-chip buffered mux/demux circuit on the digital MCM-L substrate operated at clock rates up to 9.6 GHz. The results from this study demonstrated that, with care in design and the use of low loss high frequency dielectrics, MCM-Ls are capable of operating at clock rates higher than had previously been believed possible.
The results described here are illustrative of the range of projects that we have undertaken in both printed circuit board technologies and a variety of MCM technologies. The Mayo group has tested more than twenty different MCM substrates and technologies since 1987.
During the course of both the chip carrier developments and the MCM developments, several of our projects for DARPA involved the development of complete signal processor systems. Three of the most notable of these system developments were a 1 GHz Digital Radio Frequency Memory (DRFM) in 1981-85, a 2 GHz data acquisition system (DAS) in 1987-91, and a miniaturized Global Positioning System (GPS) receiver in 1991-93.
The DRFM (Figure EP-11) was designed to digitize a radio frequency (RF) signal, store the digitized signal into computer memory, and then reproduce the same signal at a later time. The prototype processor contained 200 integrated circuits, including a GaAs Analog to Digital Converter (ADC) front end operating at 1 gigasample/sec (1 Gs/sec) with 4-bit digitizing resolution, a primary ECL memory and control section, and a 1 GHz 4-bit GaAs Digital to Analog Converter (DAC) back end. This system was implemented using the Mayo-developed chip carriers and prototyping boards described earlier, with wirewrap interconnects for the ECL section. Controlled impedance point to point wiring was used for the GaAs section.
For the 2 GHz data acquisition system, there was a requirement to develop a synchronous eight channel data acquisition system capable of acquiring signal voltage swings as low as 50 mV. This system, which was completely designed, assembled and tested at Mayo, included two different eight layer printed circuit boards (Figure EP-12) with controlled impedance interconnects and an eight layer backplane integrated into a VME chassis. This system utilized multiple logic families including GaAs and Silicon ICs. A total of 319 active components and 5890 passive components were used in the complete, eight channel system.
The miniaturized GPS receiver was an MCM re-implementation of a commercial GPS receiver employing single chip packaging and conventional printed circuit board technology (Figure EP-13). The miniaturized receiver was reduced to one double-sided MCM measuring 1.43" x 1.42" x 0.39". This MCM contains both surface mount components and bare die on both sides of the eight layer MCM substrate (Figure EP-14). Assembly and full testing and characterization were conducted in the Mayo laboratories, with full cooperation and coordination with the commercial chip vendor. Slightly improved performance was demonstrated by this module over the commercial unit. Typical power dissipation for the microminiature GPS receiver was approximately 1.3 watts. For nearly five years in the early and mid 1990s this was the smallest multi-channel GPS receiver that had ever been fabricated.
In the period between 1994 and 1997 the Mayo team, in collaboration with MIT Lincoln Laboratory, undertook the development of a prototype all-digital receiver. Operating in the 420-450 MHz band, the experimental digital receiver used a high sample rate monolithic A/D converter integrated circuit (fabricated in gallium arsenide by Rockwell Science Center) to digitize the RF signal directly, without any requirement for down-conversion of the analog signal. Mayo's task was to create a system package for the A/D converter integrated circuit and for the gallium arsenide demultiplexer chip which would not distort the incoming analog signal before reaching the input to the A/D converter, while protecting the A/D converter from the noise generated by the adjacent demultiplexer. An MCM (Figure EP-15) was created for this pair of chips tailored to the special characteristics of the A/D converter and the demultiplexer. The MCM was fabricated to our design in cyanate ester impregnated PTFE by W.L. Gore Inc. This work was described in two publications by Thompson et al. (see the publications list on this Web site).
Beginning in 1998 and continuing through 2002, the Mayo group designed and fabricated a novel all-digital receiver using an indium phosphide 7 gigasample/sec monolithic A/D converter (clocked at 2.2 GHz) and three indium phosphide demultiplexer chips to demonstrate that the reception of signals in the second (and higher) Nyquist bands was feasible. The system is comprised of two sections: The high speed section contains the A/D converter and three demultiplexer chips, and is a small multi-layer circuit board (Figure EP-16) fabricated from G-Tech (similar to conventional FR-4 printed circuit board material). Each of the four chips is mounted on a small ceramic "pallet", which is in turn mounted on and wire bonded into the small printed circuit board. This system has demonstrated the capability of a system to digitize signals from the second up to the eighth Nyquist bands, with each band approximately 1 GHz in width. The designs of the individual chip pallets and the circuit boards were shown to be capable of handling very high frequency, wideband signals for these types of applications. The low speed section contains "glue" chips and a field-programmable gate array which performs "back-end" processing on the digitized and demultiplexed data stream. The entire system, including both the high-speed and low-speed sections, appears in Figure EP-17.
Beginning in 1999 and continuing to the present, the Mayo group has been working in collaboration with HRL Laboratories on the development of sources and detectors for energy in the 83-660 GHz frequency regime. HRL Laboratories, in collaboration with NASA's Jet Propulsion Lab (JPL) and the University of California Los Angeles (UCLA), has been designing a set of HEMT circuits including a voltage-controlled oscillator, amplifiers, and frequency doublers which can be assembled end-to-end to generate sinusoidal signals from 80-330 GHz, and eventually to 660 GHz. The Mayo group has undertaken the task of packaging these components in such a way that they can be connected together on a substrate which in turn supports the delivery of DC power to the chips, and also supports the testing of the components, both individually and in a connected chain. The difficulties of preparing electronic packaging at these frequencies are formidable. Figure EP-18 illustrates a small circuit board on which is mounted a small gold-plated copper shim, which in turn supports the five small indium phosphide HEMT integrated circuits which form a 330 GHz source chain. This type of packaging is required to provide physical support and a suitable test environment for very high speed components, and has worked well. These circuits, assembled using this packaging scheme, have been demonstrated to output at least 100 microwatts of power at more than 300 GHz through testing at JPL and The Ohio State University (OSU). This packaging approach will be refined for future demonstrations of these quasi-optical systems at 330 GHz and eventually at 660 GHz.
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Page Modified: March 12, 2002
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