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The need for prototype, high frequency signal processors at
the Mayo Foundation was originally driven by a project initiated
in the early 1970s to develop a very advanced, three dimensional,
real time X-ray computed tomography (CT) scanner, referred to
as the Dynamic Spatial Reconstructor (DSR). This experimental
X-ray CT scanner generated large volumes of data which needed
to be acquired and displayed very quickly to be useful. In the
early and mid 1970s the only viable commercially available integrated
circuit (IC) technologies which could be used to fabricate special
purpose signal processors capable of addressing these required
high data rates were the two silicon Emitter-Coupled Logic (ECL)
logic families, ECL 10K and ECL 100K. Several prototype signal
processors utilizing both ECL logic families were developed during
the early and mid 1970s, the largest and most complex of which
contained more than 3000 ECL 10K components and approximately
800 ECL 100K components. This very large processor operated at
40 MHz, using a four phase clocking scheme. Several smaller processors
comprised solely of the faster ECL 100K parts operated at clock
rates in the 200-250 MHz clock rate range. Although these prototype
processors addressed a portion of the processing problems created
by the experimental tomography units being developed at Mayo,
it soon became clear that additional processing speed would be
required if such advanced computed tomography units were to become
practical and cost effective.
In the early 1980's a new technology for ICs began to emerge,
which appeared to be capable of even higher speed operation than
the silicon ECL families. This technology was (and is) gallium
arsenide (GaAs). The Defense Advanced Research Projects Agency
(DARPA) was interested in exploiting this new GaAs technology
for use in high speed signal processing applications, which had
many of the same requirements as the Mayo DSR application. DARPA
began funding Mayo in 1980 to press the state of the art of the
GaAs technology by developing Computer Aided Design (CAD) tools
that could be used to design GaAs ICs; the Mayo group also designed
a set of GaAs proof-of-concept test chips as well. Throughout
the 1980s four GaAs "pilot lines" were created to improve
the GaAs chip fabrication technology; Mayo provided design support
to all of these fabrication facilities. The transistors developed
for this first generation of GaAs integrated circuits were so-called
metal-semiconductor Field Effect Transistors (MESFETs).
One of the issues discussed in detail during the formative
stages of the GaAs MESFET chip technology, due to its immaturity
compared to silicon, was whether to develop full custom or semi-custom
integrated circuits. With full custom circuits, every transistor
and interconnect is laid out individually and compacted for optimum
speed and density. With semi-custom circuits, one or more basic
"general purpose" logic gate structures are designed
and laid out. These gates are then arrayed across nearly the entire
surface of the IC. To design a circuit function, the designer
merely interconnects these basic logic gates to make more complex
functions. The disadvantage of this semi-custom approach is that
the circuit is not necessarily optimized for speed and density;
however, the advantage is that once the logic gates have been
verified, the time and cost required to design a new function
or modify an existing design is greatly reduced in comparison
to the full custom approach. For an emerging technology such as
GaAs, the semi-custom approach greatly enhanced the chance for
first pass success and reduced the cost of design iterations;
therefore, the semi-custom approach was selected for the GaAs
Pilot Lines.
Since the early 1980's, Mayo has designed more than 175 different integrated circuits in approximately a dozen different IC technologies. The first few test circuits were fabricated by the GaAs Pilot Lines described above. These circuits contained simple arithmetic functions, such as multipliers and adders, as well as representative portions of high speed signal processor architectures (e.g., arithmetic and logic units [ALUs]). The number of gates that could be successfully implemented on a GaAs MESFET circuit, and hence the limit of these test circuits, was on the order of a few thousand (between 1000 and 6000; see Figure IC-1). The test circuits operated up to approximately 500 MHz clock rates.
One of the difficulties encountered with these first IC designs, was that no test equipment was available which was capable of verifying correct operation of these high speed circuits. Therefore, specialized GaAs chips were designed that could be used to assist in the testing of other high speed chips and multichip circuits. These specialized "tester chips" could acquire high speed serial data from an IC under test, and convert it to lower speed parallel data that could be captured by the then-existing test equipment. These designs also could convert lower speed parallel data from the test equipment into a high speed serial data stream which could in turn be applied to the inputs of a high performance IC under test. In addition, circuits were designed that would distribute a clock signal to various ICs in a multichip system design, since the distribution of high speed clock signals to many locations on a printed circuit board, reliably and in synchrony, also turned out to be a difficult problem in the design of high speed digital signal processors. The number of gates available on these GaAs MESFET chips did not increase dramatically between the early and late 1980s (remaining roughly in the 1000-10,000 gate range); however, their frequency of operation improved to approximately 1-2 GHz. By the late 1980s, GaAs MESFET chip technology had matured so much that these components could be acquired from several commercial suppliers (e.g., Vitesse Semiconductor and Triquint, Inc.; see Figure IC-2).
Additional test circuits that have been designed during the 1990s include a continuity test circuit that can be used to verify new types of assembly interconnect techniques, and a specialized chip to distribute clock signals to many locations within a large digital system. In addition, passive test circuits have been designed and fabricated to verify simulation tools and techniques with measured results. Once the simulated results have been verified, the tools are used to develop additional integrated circuits, with a much greater chance of first pass success than would be the case without any ability to predict the outcome of the design process. The present state of the art in GaAs MESFET technology will support chips containing several hundred thousand gates, and operation at clock rates at or above the 1 GHz range.
The development of new, very high speed integrated circuit technologies is continuing, and Mayo continues to collaborate with the fabricators of these new technologies. From the mid 1980s to the mid 1990s the integrated circuits industry developed GaAs integrated circuits exploiting not the MESFETs described above, but instead so-called heterojunction bipolar transistors (HBTs), which have higher fT and fMAX values (65-75 GHz) than GaAs FETs, but require more power per logic function. Working in collaboration with Rockwell and other organizations, the Mayo team designed a number of GaAs HBT chips which operated at up to 12 GHz clock rates, although the gate counts available on these GaAs HBT integrated circuits was in the range of 1000. SPPDG considers this phase of the development of high performance integrated circuits now complete; we no longer consider GaAs MESFET and GaAs HBT technologies as areas for further research for our research team. In the following paragraphs we describe those technologies in which it appears most fruitful for SPPDG to conduct future research.
During the latter half of the 1990s, a new HBT transistor technology emerged based upon Indium Phosphide (InP) HBTs rather than GaAs HBTs, with fT values initially in the range of 125 GHz (in 1997-98) and most recently with fT values reported as high as 325 GHz. Although not as mature as GaAs HBTs at present, many of the design techniques learned during our research with GaAs HBTs have been applied to the InP components. Even in its earliest manufacturable versions, InP HBTs demonstrated even more speed performance at the same or lower power levels than GaAs HBTs, because the threshold voltages for InP HBTs are in the range of .5-.6 V, compared to GaAs HBTs at 1.2 V. SPPDG has already designed and tested integrated circuits in HRL Laboratory's InP HBT process, and are employing some of those chips in advanced all-digital RF receivers (see below). We believe that InP HBT-based integrated circuits will rapidly find application in extremely high performance signal processors, in the front and back ends of satellite up- and down-links, in next-generation RF subsystems, and in the driver circuitry for next-generation lasers for long-haul fiber optics landline systems at 40 Gbit/sec (e.g., OC-768 SONET communications gear). Figure IC-3 depicts one of SPPDG's recent multi-chip layouts targeted to HRL Laboratory's InP process. The chips from this fabrication run were undergoing test at the time of this writing.
Figure IC-4 shows measured results from digital integrated circuits designed in our laboratory and fabricated for us by HRL Laboratories in one of the earlier versions of their InP HBT process, showing correct operation of this circuit at clock rates of 27 GHz. SPPDG is presently designing integrated circuits in an improved InP process which should operate at clock rates well above 40 GHz.
Integrated circuit technologies based on silicon and variants of silicon have also made remarkable progress during the past decade; we have worked with these silicon-based technologies as well. Three of these silicon or silicon-derivative technologies will be described here.
The SPPDG has implemented several signal processor designs using deep submicron bulk CMOS. Figure IC-5 immediately below is a photomicrograph of a 4096-point pipelined complex-operand (16 bits "real", 16 bits "imaginary") fast Fourier transform designed by the SPPDG and fabricated for us by a commercial bulk CMOS supplier, using .25 micrometer minimum-feature-size transistors. The architecture of this FFT chip is scalable to larger word lengths, e.g.: (24 bits real, 24 bits imaginary) using more deeply scaled CMOS transistors (e.g., .18 micrometer or .13 micrometer minimum feature size).
SPPDG has also actively been designing integrated circuits using two types of CMOS-on-oxide (SOI CMOS): fully-depleted SOI CMOS (FDSOI), and partially depleted SOI (PDSOI) CMOS. Figure IC-6 illustrates measurements from a SPPDG-designed test chip fabricated several years ago by MIT Lincoln Laboratory for us, illustrating operation of the integrated circuit at a clock rate of over 500 MHz, and a supply voltage of 2 volts (lower righthand panel). The other panels of this figure illustrate that as the supply voltage is reduced gradually to .6 V, the chip continues to function properly, albeit at a clock rate which decreases to 20 MHz, but also at dramatically lower power levels (from 25.6 mW down to .72 mW).
Figure IC-7 presents measured results from a PDSOI integrated circuit designed by SPPDG and fabricated for us by Honeywell, Inc, using their .35 micrometer minimum feature size PDSOI devices. This process is capable of supporting designs containing up to 1 million transistors, and operating at clock rates up to 600 MHz.
For a given minimum transistor feature size, other workers in this field have demonstrated a 3X to 4X improvement in speed-power product compared to bulk CMOS transistors, with the FDSOI devices perhaps 10% better than the PDSOI devices. We believe that both of these SOI CMOS processes have promise for a number of low power signal processing applications, and we intend to target designs for these technologies.
At the time of this writing we are also just beginning to collaborate with several fabricators of III-V compound semiconductors on the so-called "low bandgap" semiconductor system, including indium arsenide (InAs), gallium antimonide (GaSb), and aluminum antimonide (AlSb). This material system exhibits very high electron mobility, potentially low noise figure, very high fT and fMAX (fT values projected to exceed 500-700 GHz), low transistor threshold voltage and, because of the unique bandgap features of the three materials noted above, the likely ability to fabricate complex solid state devices with unique characteristics simply unachievable in any other materials system. Several years ago the SPPDG conducted a simulation study to identify advantages of the low bandgap materials as they would appear in digital and analog circuit designs. Figures IC-8 and IC-9 illustrate the speed-power performance of a number of different device types for known analog and digital circuits for which considerable test data exists in our laboratory for a number of device technologies, with the results from the low bandgap transistors developed from simulations. These studies indicate, as illustrated by the following figures, that the low bandgap-based transistors may exhibit an order of magnitude better performance than the best comparable existing device technology. Conversely, a large number of materials, fabrication and design issues remain to be solved with these material systems and the transistors that will evolve from them. SPPDG is strongly committed to work with the fabricators of such devices, to assist in simulations, test circuit designs and verifications, and ultimately their integration into real signal processors in a few years.
SPPDG has recently begun to work with yet another class of semiconductors, based upon the gallium nitride (GaN) materials system. GaN transistors (at the present time only FETs have been produced in this materials system), still in their infancy, are characterized by very high breakdown voltages (even the "small signal" transistors can tolerate supply voltages of 40-60 V), excellent tolerance of large overvoltages on the gates of the transistors, acceptable fT values (20-40 GHz), good noise figure, and acceptable values of IP2, IP3, and 1-dB compression points. These transistors are already being investigated for use as power devices, since they promise power-added efficiencies of 30-50% and the ability to operate at high temperatures (the GaN transistors are usually fabricated on a silicon carbide substrate, but fortunately both materials have very high thermal conductivities, which materially assists in the cooling of the transistors). Physically small GaN transistors may also find application in the low-noise amplifiers (LNAs) of RF receiver circuits, perhaps to frequencies of 10-12 GHz. Their tolerance of large gate overvoltages would allow small GaN transistors to be used to implement LNAs without the need for input voltage limiters to prevent unusually strong input signals from destroying the LNAs (as must be done at present with many such circuits). Figures IC-10 and IC-11 present measurements from the first GaN transistors to enter our laboratory, and as such illustrate the general capabilities of small power GaN-FETs, but by no means the final performance levels that can be expected from these devices as they mature.
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Page Modified: February 11, 2002
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