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Introduction
The Special purpose Processor Development Group (SPPDG) has been investigating and employing unconventional transistor and integrated circuit technologies since the late 1970s. Throughout the 1980s, we worked several integrated circuit foundries to develop gallium arsenide (GaAs) metal semiconductor field effect transistors (MESFETs), in a half dozen different varieties. During the early 1990s, we worked with several of these same foundries to develop GaAs heterojunction bipolar transistors (HBTs) and integrated circuits based on these devices. While drawing much more power and supporting much lower levels of integration than the GaAs MESFETs (hundreds of gates to slightly more than one thousand gates for the HBTs versus tens of thousands of gates for the GaAs MESFETs), the digital GaAs HBT integrated circuits were able to operate at 10-15 GHz clock rates. During the past five years, the SPPDG has concentrated on several other emerging device technologies, described below.
Indium Phosphide Heterojunction Bipolar Transistors (InP HBTs)
Throughout most of the 1990s, HRL Laboratories (HRL; formerly Hughes Research Laboratories) and TRW Space Systems Group have been developing advanced indium phosphide-based (InP) HBT integrated circuit technologies. Although not as mature as the GaAs HBT technology described above, InP is poised to become a major contributor in the high performance arena. InP HBTs represent the highest performance digital technology presently available, with divider clock rates already demonstrated to be close to 40 GHz. Ft values approaching or even slightly exceeding 300 GHz have been obtained for single HBTs from the most recent generation of such devices, which are characterized by their dramatically reduced ("scaled-down") dimensions (e.g., emitter stripe widths less than 1 micrometer). These devices exhibit extremely high performance because the mobility and saturation velocity of electrons in the GaInAs base and collector regions is higher than in Si, SiGe, or GaAs. InP-based HBTs also have good current gain at very low current densities due to low surface recombination velocity. This feature also leads to low phase noise, which is important in the design of mixed signal integrated circuits combining analog and digital functions on the same chip, such as analog-to-digital converters (ADCs). InP exhibits a thermal conductivity almost 50% greater than GaAs. The improved thermal conductivity reduces the sensitivity of individual devices to temperature, which is another important feature for mixed signal circuits.
One of the most important advantages of InP-based HBTs is a low base-emitter turn-on voltage, which minimizes the required supply voltage, which in turn reduces circuit power consumption. The turn-on voltage of InP HBTs (~.2-.4 V) is not only much lower than for GaAs HBTs (~1.2 V), it is also lower than Si bipolar (~.6V), thereby enabling direct compatibility between Si bipolar circuit designs and InP HBT circuit designs. This feature will enable the insertion of InP circuits into critical sections of existing designs, while enabling more standard Si bipolar circuits to be used in less critical sections. Several companies producing integrated circuits for consumer electronics and wireless applications are investigating the use of, or are already manufacturing, InP HBT-based integrated circuits.
It must be pointed out that because InP technology is less mature than GaAs or SiGe, integrated circuit complexity is presently limited to 1000-2000 transistors; however, over time, the transistor counts of InP HBT integrated circuits should definitely achieve mid-LSI levels. This technology should be of interest to researchers working in the fields of high speed communications and encryption, direct digital processing of wide bandwidth signals such as radar, and the design of high performance mixed signal integrated circuits. InP HBT-based integrated circuits are being fabricated by HRL Laboratories and TRW, among others.
Low Power Silicon-On-Insulator (SOI) Transistor Technology
The SPPDG has been working with low power silicon-on-insulator CMOS (SOI CMOS) transistors since the mid-1990s, in two varieties: fully depleted SOI and partially depleted SOI. Both flavors of SOI CMOS are well suited to low-power, high-speed CMOS applications. The addition of an insulating layer between the active devices and the Si substrate reduces the parasitic capacitances associated with each device and results in very short propagation delays and high operating frequencies relative to conventional bulk CMOS, allowing this technology to compete for applications that require both analog and digital circuits (including on the same chip) that must function in the gigahertz range at very low power. This reduction in parasitic capacitance is an essential feature of SOI, and it leads directly to the 2X-3X speed advantage that both types of SOI exhibit in comparison to conventional bulk silicon (assuming equivalent transistor feature sizes). MIT Lincoln Laboratory is presently fabricating "fully-depleted" SOI CMOS circuits with gate lengths ("as drawn") of .18 micrometers. Functional circuits operating greater than 2 GHz with a 2 V power supplies have been fabricated and demonstrated on numerous occasions using a somewhat older .25 micrometer gate length technology. This speed improvement can also be traded off against minimum feature size, e.g. an SOI process with a 0.35 um design rule can offer speed performance comparable to that of bulk silicon with a 0.25 um design rule, allowing a more mature and cost-effective fabrication technology to be used to obtain the same performance. Both IBM and Honeywell in Minneapolis are continually evolving partially depleted SOI CMOS; Honeywell is presently fabricating SOI CMOS integrated circuits with .35 um as-drawn minimum feature sizes, at 1 million gate complexity.
The commercial availability of SOI wafers with specifications close to those of bulk silicon and at competitive prices, along with their compatibility with standard CMOS processing techniques, allows SOI technology to provide cost effective solutions to a variety of applications. The major impediment to the use of SOI to obtain VLSI levels of integration is its reduced ability to remove heat from the active regions of the circuit due to the lower thermal conductivity of silicon dioxide compared to that of bulk silicon. However, this constraint will become less of a problem as supply voltages continue to be reduced. SOI's isolation from the substrate permits stable operation in the low-voltage regime - a 256K SRAM on SOI was demonstrated to function at 1.2 V, while a bulk silicon cell with the same design would not operate with a 2 V supply.
CMOS and Silicon Germanium Bipolar HBT Technologies in Combination
The combination of silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) with conventional bulk CMOS devices (the combination of HBTs and CMOS transistors on the same integrated circuit is referred to as BiCMOS) has the potential to enable very complex "mixed-signal" systems on single integrated circuits. The graded germanium in the base of SiGe HBTs increases the emitter efficiency and decreases the base transit time. Since the base transit time of a bipolar transistor is a major component limiting the intrinsic device speed, this reduction results in devices with production values of unity gain bandwidth product, fT, of up to 120 GHz. Experimental devices have recently been announced by IBM exhibiting ft greater than 200 GHz. These device characteristics suggest that amplifiers and oscillators operating at up to or slightly above 20 GHz and 40 GHz, respectively, are achievable in this technology. This high-frequency performance, significantly greater than that of homojunction silicon BJTs, is already allowing SiGe to compete with GaAs HBTs. In addition, SiGe can provide these application solutions at the low costs associated with high volume, large diameter silicon wafer processing. For a number of years IBM Corporation has been fabricating SiGe HBTs on the same integrated circuits and in the same fabrication facilities as conventional bulk CMOS devices, creating a SiGe BiCMOS integrated circuit capability with simultaneously the best features of very high transistor count bulk CMOS devices (several million gates if required) with voltage-matched SiGe bipolar transistors for "fast sections" of the same circuits. The SPPDG has been working with IBM on this technology for more than five years; we have recently designed, IBM has fabricated, and we are testing BiCMOS integrated circuits using IBM's 7HP technology (bipolar transistors with fT values of 120 GHz, CMOS devices with as-drawn gate lengths of .18 micrometers). To the present we have participated in a number of fabrication runs of SiGe bipolar and BiCMOS integrated circuits, with substantial success--with a very few exceptions, the chips have achieved first-pass fabrication success, with as-measured operating characteristics virtually identical to the predicted performance based on simulations.
This mixed Si, SiGe, BiCMOS environment presents several interesting possibilities for both device researchers, chip designers of digital, analog, and mixed mode functions, and systems architects. IBM's earlier 5 HP process (HBTs with fT values of 47 GHz and CMOS devices with .5 micrometer as-drawn gate lengths) is available through the MOSIS integrated circuit foundry service.
Antimonide-Based Compound Semiconductors
As of Summer 2001, DARPA is initiating a four-year "Antimonide-Based Compound Semiconductor (ABCS) program to evolve a new family of integrated circuit technologies referred to as "low-bandgap" or "antimonide-based" compound semiconductors. These heterojunction bipolar and high electron mobility field effect transistors (referred to as "HEMTs" or "MODFETs") exploit the unique (and, for purposes of transistor design and fabrication, complementary) bandgap characteristics of several compound semiconductor materials: indium arsenide (InAs), gallium antimonide (GaSb), and aluminum antimonide (AlSb) (the materials system is also referred to as the "6.1 Angstrom materials system, since all three materials exhibit crystal lattice constants in the 6.1 Angstrom range). The unique combination of bandgaps and band offsets in these three materials, combined with the extremely high mobility of electrons in InAs, have encouraged the design or postulation of a number of types of novel transistors and other types of active devices (e.g., detectors) that are not realizable in any other materials system. For example, early attempts are being made to develop HBTs in this materials system with fT values exceeding 500 GHz, and FET-type devices with fT values exceeding 700 GHz. Further, it appears that it may be possible to operate circuits constructed with these transistors at supply voltage levels as low as 1 volt, resulting in significant reductions in power consumption for digital and analog circuits made with the low-bandgap transistors, in comparison to similar circuits manufactured with silicon, GaAs, or SiGe transistors. Finally, for reasons having to do with the device physics characteristics of this materials system, low-bandgap transistors are likely to exhibit very low (excellent) noise figure, which will make them useful for the implementation of high-quality low noise amplifiers (LNAs) operating at very high frequencies (up to, and possibly beyond, 94 GHz). By the end of the four-year ABCS program, it is planned to be able to manufacture integrated circuits with at least several thousand transistors. A very large number of electronic systems can benefit from transistor development that will emerge from the ABCS program.
The SPPDG is heavily committed to the ABCS program. We are collaborating actively with TRW, HRL Laboratories, and Rockwell Scientific Company to bring the ABCS technologies to fruition.
Gallium Nitride Transistor Technology
In contrast to the low-bandgap material systems described immediately above, so-called "wide bandgap" material systems (with crystal lattice constants much lower and material bandgaps much higher than those of silicon) are being exploited for an entirely different type of transistor. The two material systems under consideration are gallium nitride (GaN) and silicon carbide (SiC). The SPPDG has begun test and evaluation of initial-sample GaN transistors fabricated by HRL Laboratories. The wide bandgap transistors (all of which, to date, are n-type FETs) are characterized by moderate fT values (20-30 GHz presently), very high breakdown voltages (kilovolt breakdown voltages have been demonstrated for power FETs, and 40-60 volt breakdown voltages for signal amplifier transistors) and acceptable noise figure values. The small transistors can tolerate several tens of volts of input swing on their control gates, and both GaN and SiC devices exhibit excellent heat removal characteristics (the GaN devices are frequently grown on SiC substrates, which have very high thermal conductivity). Future power FETs in these material systems are projected to exhibit very high power added efficiencies (approaching 30-50%) at S-band for SiC transistors and into the X-band frequency range for GaN devices. The large FETs will find systems applications as the power devices in the transmit/receive (T/R) modules of next-next generation radar systems. The smaller GaN transistors are very attractive as the building blocks of low noise amplifiers for the receiver amplifier chains in radar T/R modules, because the ability of the transistors comprising the LNA to withstand high transient overvoltages on the gates of the transistors makes them robust in situations where very high radio frequency (RF) pulses impinge on the surfaces of the antenna. This robustness at the transistor level may make it possible to omit the "overvoltage limiter" circuits typically incorporated into the receiver chain of a T/R module between the antenna element and the LNA, thereby improving the sensitivity of the T/R module receive chain while decreasing the overall parts count the receiver chain.
During the summer of 2001, DARPA initiated a new program in GaN materials and transistor technology. The Mayo SPPDG plans to be involved in the new GaN program if at all possible, thereby complementing our initial work in the test of early GaN transistors.
Copyright © 1984-2001 by Mayo Foundation. All rights reserved.
Page Modified: October 11, 2001
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