Over the years the SPPDG has conducted a number of complete system development projects, the first as long ago as the early 1970's (see History section). During the 1980's the group developed a Digital Radio Frequency Memory (DRFM) containing a 4-bit, 1 gigasample/second gallium arsenide A/D converter and 200 other commercial components. During the early 1990's we developed an eight-channel fully-synchronous data acquisition system, with each channel collecting digital data at 2 gigabits/second; channel sensitivities allowed data collection from signals with amplitudes as small as 50 mV. From 1991 to 1993 we developed a very small (for the time period) six-channel global positioning system receiver, using unpackaged integrated circuits mounted on both sides of a laminate (i.e., organic) multichip module (MCM); the system consumed 1.3 Watts. Figure below is a front-and-back photo of the global positioning system (GPS) receiver, which held the world’s record as being the smallest such system for nearly five years. The unit was designed, simulated, and assembled in our laboratory using integrated circuits acquired in a collaborative project from Motorola, Inc.
Physical circuit functions of top and bottom surfaces on stage two micro-miniature GPS receive using Mayo Foundation design and Motorola chip set.
In the period between 1994 and 1997 the Mayo team, in collaboration with MIT Lincoln Laboratory, undertook the development of a prototype all-digital radar-like receiver. Operating in the 420-450 MHz band, the experimental digital receiver used a high sample rate monolithic A/D converter integrated circuit (fabricated in gallium arsenide by Rockwell Science Center) to digitize the RF signal directly, without any requirement for down-conversion of the analog signal. Mayo's task was to create a system package for the ADC integrated circuit and for the gallium arsenide demultiplexer chip which would not distort the incoming analog signal before reaching the input to the ADC, while protecting the ADC from the noise generated by the adjacent demultiplexer. An MCM was created for this pair of chips tailored to the special characteristics of the ADC and the demultiplexer. The MCM was fabricated to our design in cyanate ester impregnated polytetraflouroethylene (PTFE) by W.L. Gore, Inc. Figure below depicts the two-compartment leaded flat pack, illustrating installation of the A/D converter chip in the leftmost cavity, and the demultiplexer in the rightmost cavity.
Top view of Mayo-designed digital receiver multichip module containing Rockwell gallium arsenide 8 bit 2 Gs/sec analog-to-digital converter chip and 9:72 demultiplexer chip.
Beginning in 1998 and continuing through 2002, the Mayo group designed and fabricated a novel all-digital receiver using an indium phosphide 7 gigasample/sec monolithic A/D converter (clocked at 2.5 GHz) and three indium phosphide demultiplexer chips to demonstrate that the reception of signals in the second (and higher) Nyquist bands was feasible. The system is comprised of two sections: The high speed section (referred to as the digitizing section), located on one of a pair of circuit boards (each of dimensions 4” x 4.25”) “sandwiched” together, contains the A/D converter, a demultiplexer chip, and a clock distribution chip; all three chips were fabricated in an indium phosphide HBT technology for us by HRL Laboratories. The second sandwich board (referred to as the processor board) contains a Xilinx Vertex II-8000 Field Programmable Gate Array (FPGA) and seven configuration memory chips. Figure below is a photo of the sandwich board pair.
Digitizing module and signal processor modules.
The figure below is a six-panel frequency domain data chart, with each panel generated from a fast Fourier transform of the output data, executed by the FPGA installed on the processor board. The upper three panels illustrate the results of a two-tone detection test, with the two tones separated by 100 MHz; the lower three panels illustrate a similar test, but with the tones separated by 5 MHz (the photo below does not resolve the two separate frequencies as separate “lines” on the frequency plots, but the data clearly show the separation). The system was able to resolve the two tones in all cases, even down to the 5 MHz separation, in every band from the first to the eighth Nyquist bands, with each Nyquist band 1.25 GHz in width. The revisit rate of the scanning process in any given Nyquist band is 100 nsec.
First, second and eighth Nyquist band sampling of dual tone input signals applied to HRL Laboratories indium phosphide 3-bit ADC operating at 2.5 GHz sampling rate using two most significant bits.
Beginning in 2002, the Mayo team developed processor systems, housed in rack-mountable drawers, that could accept digital optical data streams at OC-192 rates (9.6 gigabits/second), convert the optical data stream to electrical signals, conduct processing operations on the electrical data stream (using seven large Xilinx Vertex Field Programmable Gate Arrays in each chassis), reconvert the processed electrical stream back into an optical bit stream, and retransmit the optical signal onto an output fiber. Although the Mayo group typically does not fabricate more than one or two examples of any given processor, this project was an exception, since the sponsor requested that additional systems be fabricated after the first two had been proven to work as intended. A rigorous test of these systems is illustrated in Figure below, in which an optical bit stream generated by an Agilent bit-error-rate detector (BERT) system was run in series through 5 consecutive chasses (seven chasses appear in the Figure, but only the five leftmost stacked units were tested in this particular run). The entire set of five systems operated continuously at 9.6 gigabits/second for 12 hours without a single detected bit error.
Optoelectronic system prototype limited production testing and final assembly.
