The SPPDG found itself in need of specialized electronic computer aided design (ECAD) tools to assist in the design and simulation of high performance non-silicon digital integrated circuits (ICs), and systems constructed with these specialized chips, in the early 1980's. There were few ECAD tools and NO design frameworks at that time, so it was necessary to develop the appropriate tools and supporting framework to assist in the design and implementation of high clock rate digital signal processors. The Mayo-developed tools became an integrated system called MagiCAD.
The SPPDG used MagiCAD almost exclusively for semicustom gallium arsenide (GaAs) IC design from the mid-1980's until 1998. By that time, simply maintaining the complex infrastructure of an ECAD system became a significant effort. Meanwhile most of the major commercial ECAD vendors had improved their tool suites significantly, adding flexibility and support for "deep sub-micron" features which were similar to the design issues in high speed GaAs IC design. Today Mayo has many different commercial ECAD tools for semicustom IC, printed wiring board (PWB), and multichip module (MCM) design available in-house.
The SPPDG has continued to develop and deploy a number of ECAD application programs and integration scripts to enhance the performance of the various design systems in use today. These tools range in complexity from simple scripts (e.g., generate piecewise linear SPICE models for pseudo-random bitstreams) to complete engineering tools based on new techniques and algorithms (e.g., new measurement de-embedding analysis tools). Once new algorithms and techniques are implemented, they are generally documented inpublications.
Electromagnetic Modeling
One important component of high clock rate system design is attention to the details of the electronic packaging into which the high performance integrated circuits are installed. Mayo developed a series of electromagnetic (EM) simulation tools beginning in the 1980's. Early transmission line analysis "field solvers" predicted the parasitic capacitances and inductances of controlled impedance transmission line structures.
However, simply predicting parasitic capacitances and the resulting crosstalk was not sufficient to completely understand signal behavior between high speed ICs. It was necessary to develop waveform simulators that could account for all of the crosstalk, dispersion, and reflection characteristics of the interconnect: effects which are highly frequency dependent, and are not well modeled by SPICE-like time domain simulators. The Mayo team created a series of frequency domain waveform simulators that could predict all of these effects in a closed form solution.
To accommodate "real world" complex interconnect structures, the Mayo SPPDG created the Networking Tool, which can simulate multiple interconnected coupled transmission line environments with an arbitrary topology and a variety of discontinuities. The Networking Tool has been successfully employed to model a number of single-chip IC packages and multiple chip system applications.
The first set of waveform simulators developed at Mayo are based on the Telegrapher's Equations, which rely on the so-called quasi-TEM assumptions. These assumptions simply imply that the electric and magnetic field components of the moving wavefront are orthogonal to the direction of wavefront propagation in the transmission line. These assumptions are considered valid whenever the signal wavelengths are significantly larger than the cross-sectional dimensions of the transmission line. To assure that we remain within the region of validity for these assumptions, we generally constrain the use of these techniques to bandwidths of 2-5 GHz, although the limitations also scale with smaller interconnect geometries.
New developments in transistor technology have continued to push analog system frequencies and digital clock rates well beyond the realm of the quasi-TEM assumptions upon which the early transmission line and waveform analysis were based. As digital clock rates enter the 10-100 GHz range, it is necessary to accurately model the electromagnetic behavior of circuits from DC to (approximately) five times the system clock rate. This is accomplished by the application of full-wave algorithms which accurately model electromagnetic behavior without limitations on frequency.
Mayo has developed a full-wave transmission line simulator based on the Finite Edge Element Method (FEEM), which is derived from vector finite element methods. This tool has been shown to be about ten times faster than traditional Finite Element Method programs. This makes it possible to directly simulate all frequencies of interest, instead of relying upon numerical extrapolation techniques
These Mayo-developed transmission line simulators, and many commercial analysis tools, provide similar capabilities, but dissimilar and often difficult user interfaces. Mayo developed a new transmission line modeling framework and a simplified user interface for creating 2-D transmission line models and controlling several EM simulators. The new tool, dubbed TNT, streamlined the creation of transmission line cross section models for HSPICE or other system simulators. TNT is available in source code and executable forms athttp://mmtl.sourceforge.net/.
TNT transmission line simulator main window with example two conductor microstrip cross section.
The SPPDG has continued to develop additional EM tools for analysis of singled-ended and differential transmission line and serial link subsystems. The Xmission tool, for example, uses TNT simulations as a baseline, and tunes the transmission parameters using measurement data to produce highly accurate system simulation models.
Power and Ground Plane Modeling
The characterization of "noise" in the power distribution planes of a MCM or PWB is now becoming an area of concern to the designers of commercial electronics systems, such as microprocessors operating at 200-5000 MHz clock rates, primarily because power and ground noise can dramatically affect electronics systems operating at these rates. This topic has been an area of concern to the designers of extremely high performance digital and mixed signal military systems throughout this decade. However, until recently, very little progress has been made in its solution.
The Mayo team worked aggressively on these problems from 1992-2002, and developed a number of efficient fast-quasi and 3-D full-wave power/ground plane noise simulators for frequencies up to 100 GHz using generalized Z- and S-parameters employed in microwave network analysis. These present first-generation algorithms and EM tools are being extended to higher frequencies with improved accuracy, and include measurement de-embedding, full-wave active device models, and more complex physical geometries.
As we applied the early power and ground plane noise modeling tools to a number of problems, we have come to understand that the circuit concepts underpinning traditional intuition about power and ground plane noise have been completely wrong. Furthermore, the engineering "rules of thumb" that we have developed to suppress noise in the power systems, based on intuition and trial and error, are also sometimes wrong. We have discovered, for example, that simply choosing the correct component placement on a PWB can have a very dramatic effect on the amount of power and ground plane noise created in the system. We published this example of a two chip system, where clever selection of component placement suppresses the power system noise over wide ranges of frequency.
Our most recent work in power and ground modeling has been at the level of the individual IC. The core of modern deep-submicron ICs operate on nominal voltages around 1 Volt, and with edge dimensions as large as 20 x 20 mm, containing 200 million or more transistors, “ground bounce” and “rail collapse” issues can seriously degrade performance. We are working to understand and quantify these on-chip power distribution problems through design and laboratory testing of large CMOS test chips and through the development of analytical and empirical models that can be used in conjunction with commercial IC design tool suites.
Comparison of on-chip dynamic voltage supply VDD droop across 223 million transistor ASIC showing initial design and final design with added decoupling capacitance and enhanced VDD power grid.
Future Electromagnetic Modeling Research
Several new guided wave EM simulation technology areas still need to be addressed for future generations of electronics systems. A new generation of efficient full-wave algorithms and simulation tools need to be developed to characterize emerging-technology semiconductor devices and their immediate environment. New tools are needed to analyze device-to-device and device-to-interconnect coupling of entire digital standard cells (several to many transistors) while maintaining full-wave fidelity above 100 GHz. Full-wave circuit analysis will be needed to design digital and mixed signal integrated circuits. New power delivery system design tools will be required to ensure that multichip systems will function correctly at speed. In addition, a better understanding of the high frequency electrical non-linearity of present-day packaging is needed to develop future generations of electronic systems.
It should be noted that development of electromagnetic modeling tools is one of the most difficult endeavors in present day ECAD technology. Literally years of effort must be invested in the development of algorithms and mathematical techniques that will accurately model a subset of the EM problems in high speed system design. Once the algorithms have been created and tested in limited simulation programs, the ECAD tool development team must generalize the algorithm, add error handling and code to predict numerical accuracy, create the graphical and non-graphical user interfaces, and tie the simulator into the design framework for the electrical engineers. Once the new simulation tool is in place, the results of the simulations must be carefully verified as its use is extended to each new problem. EM simulators developed by the Mayo team have always been verified by fabricating and testing physical structures designed exclusively to determine the accuracy of the simulation tool. By using a closed loop of simulator development, simulation, and testing, Mayo has been able to identify and correct shortcomings in the simulation tools as we applied them first to PWBs, then to MCMs, and most recently to on-chip interconnects.
