During many years of developing single-chip packages (1970's and 1980's), it became clear to the members of the SPPDG that irrespective of the quality of the design of any given single-chip package, the package imposed significant electrical performance constraints on the chips because of residual parasitic inductance and capacitance, and on the circuit boards and the resulting signal processor systems because of the large amount of real estate consumed by the packages (package areas were 15-60 times the areas of the chips themselves). The solution to these electrical and mechanical problems was the complete elimination of the integrated circuit (IC) package, and a conversion to multichip packaging approaches such as hybrids and multichip modules (MCMs), which may be thought of as microminiature circuit boards, on which bare integrated circuits are installed and connected to extremely narrow traces on the surface of and buried within the MCM.
In the 1980's, the SPPDG recognized this need and began investigating MCM packaging for high performance applications. With little information or test data available on the high performance aspects of the various MCM technologies, the SPPDG began a large study in the late 1980's to characterize and compare numerous MCM technologies, including laminate (MCM-L), ceramic (MCM-C), and deposited (MCM-D) processes. To provide a much needed service to industry and government collaborators and to prevent duplicating the efforts of other researchers, the SPPDG concentrated on characterizing the high frequency performance of MCM technologies.
First multichip module (MCM) designed and tested in the SPPDG laboratory (1988-89) included both passive interconnect structures (left) and active circuit regions (right).
To aid in the study, a set of structures was developed specifically for high frequency characterization and comparison. These structures have since been fabricated in nearly two dozen MCM technologies. When possible for each technology, Mayo designed the substrates, paid for the fabrication, worked within the vendor's design rules, and fully characterized the electrical performance of the resulting structures. A vector network analyzer (e.g., HP8510 with a frequency range from 45 MHz to 26.5 GHz) and a time domain reflectometer (e.g., Tek11801 with a <35 psec risetime) were utilized when measuring these structures. At present our laboratory contains network analyzers with upper frequencies of 110 GHz and 220 GHz, and we employ the newest generations of Tektronix and Agilent oscilloscopes and spectrum analyzers.
Utilizing the resulting measurement database, the SPPDG is able to compare different technologies for performance, routing density, inter-signal coupling (i.e., crosstalk), and manufacturing tolerance. In addition, the SPPDG is able to provide feedback to the substrate vendors with information on their technology's performance relative to others and methods to improve their technology.
To understand the reasons for the variations in the different technologies, the SPPDG physically makes cross sections of example substrates, polishes the substrate edges, and takes either photomicrograph or scanning electron microscope (SEM) images of the cross sections. Views of the vias, power planes, and transmission lines provide significant insight into the manufacturing tolerances and electrical performance of each technology. In addition, atomic force microscopy (AFM) provides detailed images of surface height variation.
Scanning electron microscope (SEM) photographs of typical multichip module (MCM) via structures.
Numerous and quite diverse MCM technologies were explored, including:
"Chips first" approaches, in which the IC die are attached to an unprocessed ceramic support substrate, whereupon interconnect metalization is fabricated on top of the die, resulting in modules with all of the ICs buried beneath the interconnect and the ground and power planes, and with no bond wires whatsoever.
"Flip Chip Attach" approaches, in which the IC die are mounted face down directly on top of an MCM substrate, again with no bond wires.
"Chips Last" approaches, in which the IC die are attached face-up on a previously patterned MCM substrate, and then wire bonded to the electrical contacts on the substrate using either ball bonding or wedge bonding.
A technology containing prefabricated signal interconnect "links", allowing the rapid turnaround of MCMs with one or two interconnect personalization layers.
We also explored the incorporation directly into the MCM substrates of passive electrical components such as resistors, capacitors and inductors, thereby conserving the surface areas which would normally have to be committed to discrete passive components.
Multichip module with embedded passive structures.
Other demonstrations of MCMs containing high performance integrated circuits have included a small family of sixteen chip gallium arsenide (GaAs) demonstration modules, each of which utilizes sixteen, 2000 gate GaAs configurable gate arrays; each 16-chip module had a total of 520 I/O. This 16-chip design was used in numerous studies as an active circuit benchmark in many MCM technologies. A portion of this 16-chip design was also implemented in two different flip chip attachment technologies.
MCM substrates for 12 GHz demonstration circuits.
In the mid 1990's the Mayo group undertook an investigation of the high-frequency performance of MCM-L technology, with the goal of demonstrating its appropriateness for the development of all-digital receivers operating at analog frequencies in the 4-6 GHz range, and clock rates in the 8-12 GHz range. Several test modules were developed, including a unique "paired" substrate: The upper half of the pair contained a mixed-signal circuit, while the bottom half of the pair contained all-digital chips. The mixed-signal substrate contained sites for a "mockup" of an all-digital receiver including a low noise amplifier, three separate analog-to-digital converter part types, demultiplexers; and two low noise amplifiers, one with and one without an integrated filter. The digital substrate contained sites for a 7-chip NEL circuit, a 2-chip clock circuit, a 4:1 multiplexer, a 1:4 demultiplexer, and a 1K gallium arsenide gate array. The MCM substrates were fabricated from a cyanate ester-impregnated polytetraflouroethylene (PTFE) dielectric material. The seven-chip buffered mux/demux circuit on the digital MCM-L substrate operated at clock rates up to 9.6 GHz. The results from this study demonstrated that, with care in design and the use of low loss high frequency dielectrics, MCM-Ls are capable of operating at clock rates higher than had previously been believed possible.
Advanced packaging work continues to the present. More recently we have worked with polyimide BCB, and most recently, liquid crystal polymer (LCP) substrates. We have used, and continue to explore area-array flip-chip attachment of integrated circuits to MCM substrates using fine-pitch solder and gold bumps, and thermocompression, ultrasonic, and adhesive bonding methods. The figure below depicts a pair of matched multiplexer and demultiplexer test fixtures, each of which consists of an LCP substrate to support the high speed signals and a connection to a conventional printed circuit board for lower speed signals. The multiplexer and demultiplexer integrated circuits were stud-bumped and flip-chip attached to the LCP substrates using anisotropic conductive film. The high speed inputs and outputs were routed to V-connectors attached to the edges of the substrates. This set of LCP-based substrates was designed to support the multiplexer and demultiplexer integrated circuits operating at 40-80 gigabits/second data rates.
Photograph of assembled 80 Gbps multiplexer and demultiplexer liquid crystal polymer test boards.
The figure below illustrates the waveforms for the multiplexer operating at 70 gigabits/second.
Measured data from 80 Gbps 16:1 multiplexer circuit showing maximum frequency operation at 70 Gbps.
In order for the SPPDG to gain full access to the MCM vendors' technologies, much of the MCM packaging analysis work has been performed under nondisclosure agreements, and thus has not been releasable to the general electronics community. Nonetheless, when possible, the SPPDG publishes papers and reports in public fora and continues to expand the study with new electronic packaging technologies as they arise.
