Since the early 1980's, the Mayo team has designed nearly 300 integrated circuits (ICs), in a very large number of III-V compound semiconductor technologies, and in bulk silicon CMOS and in silicon-on-insulator CMOS SOI. Digital circuit designs have ranged from relatively simple adder and multiplexer circuits to complex signal processors and system support functions. Analog circuits have included analog-to-digital converters (ADCs), direct digital synthesizers, transmit/receive circuits, equalizers, amplifiers, and mixers. Some circuits have been designed to evaluate an emerging transistor technology, while others are intended to implement a prototype system. Because this research group was founded to develop the highest-possible-throughput signal processors for large-data-volume requirements (a goal which has continued to the present), we have always concentrated on exploiting IC technologies that promised the ability to develop very high clock rate digital functions, and more recently, high-center-frequency analog and mixed-signal components.
In the early and mid 1970's the group employed the then-fastest commercial off-the-shelf IC technologies, the several varieties of silicon emitter-coupled logic (ECL), to develop special-purpose digital signal processors, both small (~100 ICs) and complex (~3000 ICs) to handle large volumes of X-ray computed tomography data (see the “History” section of this web site). By the early 1980's we began to design specialized non-commercial digital ICs, initially and throughout the 1980's, in gallium arsenide (GaAs) metal-semiconductor FET (MESFET) technologies; these ICs were fabricated for us by Rockwell Science Center (now part of Teledyne), McDonnell Douglas, Hughes Research Laboratories (now HRL Laboratories), AT&T, and TRW (now Northrop Grumman Space Technologies). Throughout the 1980's we attempted to balance gate speed with integration levels, and by the late 1980's, had designed and tested GaAs ICs with 5000-7000 gates (not large by CMOS standards even then), but operating in the .5-1 GHz clock rate range.
In the early 1990's we worked with the same companies as in the prior paragraph to develop GaAs heterojunction bipolar transistor (HBT) chips, with transistor counts only in the hundreds but operating at clock rates up to 10-12 GHz. These ICs were ideal for use as high-speed counters, specialized multiplexers and demultiplexers, and so on. Some of these ICs were intended only as “test chips”, but some were incorporated into highly specialized signal processors and actually fielded.
By the mid 1990's the speeds of CMOS devices were increasing to a level that piqued our interest. Our first attempts to design very high throughput silicon CMOS ICs were in collaboration with IBM Watson Research Center to exploit IBM’s emerging silicon-germanium (SiGe) BiCMOS technology (known then as “5 HP”). The advantage of SiGe BiCMOS was and is the ability to combine large numbers of bulk CMOS transistors with a smaller number of SiGe compound semiconductor bipolar transistors, using the slower high-transistor-count CMOS transistors for low-to-mid speed complex signal processor functions, and using the bipolar transistors for high-clock-rate front and back ends attached to the CMOS functions, including both digital and analog functions. We have worked with successive generations of IBM’s SiGe BiCMOS, the most recent of which is their 8 HP technology. We have also worked with other companies offering SiGe BiCMOS as well, selecting the particular fabrication process depending on the needs of the specific ICs being designed. The figure below illustrates the layout of a 4-bit "flash" A/D converter chip designed in our laboratory using IBM’s 8T SiGe process (the “8T” designation means that in this particular case only the bipolar transistors were employed in the design, i.e., without use of the .13 micrometer CMOS devices).
Mayo designed 4-bit gray code flash ADC using SiGe bipolar 8T technology.
The figure below is a multi-project IC designed in our laboratory, in the IBM 8 HP technology (i.e., employing both the bipolar and the CMOS transistors as appropriate) illustrating a large number of different functional components implemented within the same SiGe BiCMOS subreticle.
Layout of Mayo multi-project reticle implemented in IBM 8HP SiGe BiCMOS technology.
In the late 1990's we began to design digital ICs using bulk CMOS as well as the more exotic technologies. In the 1999-2001 time frame we designed, had fabricated, and tested a single-chip fully pipelined, programmable 4096-point complex (16 bits real, 16 bits imaginary) fast Fourier transform (FFT) IC that could execute a 4K-point complex FFT in 20 microseconds, consuming slightly over 2.5 Watts (see figure below).
Final layout of Mayo-designed fully pipelined fast Fourier transform (FFT) chip.
The IC, which contained 8.2 million .25 micrometer transistors, was capable of executing under program control, in fully pipelined mode, any FFT length from 4K down to 4 points, without loss of pipeline efficiency. The algorithm for the FFT chip was developed by our collaborator Dr. Earl Swartzlander of University of Texas at Austin, with whom our research group has collaborated since the early 1970's. The IC was thoroughly simulated, was a first-pass fabrication success (fabricated for us by LSI Logic, Inc.), and was tested in the laboratory and then actually installed into a specialized prototype system, where it performed as intended. The figure below illustrates, in the upper panel, a full floating point Matlab simulation of the frequency domain output from a 2048-point FFT algorithm; the middle panel of this figure illustrates the results from a fixed precision simulation of the pipelined FFT algorithm as it was to be embodied on the IC; the lower panel presents actual measured results from the FFT chip itself, with the same input data used in the two simulations. The results across all three panels are essentially identical. Finally, we wish to comment that the architecture of this FFT chip is scalable to larger word lengths, e.g., (24 bits real, 24 bits imaginary) using more deeply scaled CMOS transistors (e.g., .13 micrometer or .065 micrometer minimum feature size).
Comparison of simulated results to Mayo-designed pipelined FFT chip measured results.
We have also designed integrated circuits in various versions of CMOS on oxide, or CMOS SOI. Several such chips have been fabricated for us by MIT Lincoln Laboratories. Figure below depicts several ICs designed by our team using MIT Lincoln Laboratory's .18 micrometer fully depleted CMOS SOI process; two of the chips are Ka-band (35 GHz center frequency) LNAs, and the third is a Ka-band RF switch (note also the device characterization structures, used to measure transistor performance and to create device models for this particular process).
Physical layout of Mayo test chip implemented with MIT-LL 0.18 mm fully depleted silicon-on-insulator (SOI) CMOS RF07 technology.
In the late 1990's and continuing to the present, we have also explored the use of III-V compound semiconductors even more “exotic” than GaAs. We began designing indium phosphide (InP) integrated circuits in the late 1990's, work that continues to the present. In addition, since 2002 we have designed IC’s in the antimonide compound semiconductor (ABCS) technologies as well. The IC’s from both of these technologies have been fabricated for us by our collaborators at HRL Laboratories, Rockwell/Teledyne, and Northrop Grumman Space Technologies. The InP transistors yield the highest overall clock rates and (for analog chips) the highest center frequencies, whereas the ABCS transistors yield slightly lower performance than the InP devices, though at significantly lower power levels. Figure below is a layout of a Mayo-designed ABCS test chip, fabricated for us by Rockwell/Teledyne, containing four different low noise amplifiers (LNAs) targeted for W-band (94 GHz).
Physical layout of Mayo test chip implemented with Rockwell Scientific (RSC) InAs channel high electron mobility transistor (HEMT) technology (Fabrication 3).
The figure below depicts the layouts of two slightly different designs for a divide-by-2 integrated test chip fabricated in Rockwell/Teledyne's InP heterojunction bipolar technology. The chip layout on the left of the figure includes a clock buffer function, while the one on the right does not.
Layout of Mayo-designed divide-by-4 circuits in indium phosphide (InP) heterojunction bipolar transistor (HBT) technology from RSC.
The figure below shows spectrum analyzer plots of the output from these ICs in the Mayo test laboratory. We do not own test equipment fast enough to capture the actual waveforms; thus, spectrum analyzer is employed to search for the correct frequency components that would be expected to be generated by the counted-down output waveform. The 150 GHz sinusoidal clock signal was generated by a Backward Wave Oscillator and fed to the clock inputs on the ICs under test.
Output spectrum of Mayo-designed divide-by-4 circuit fabricated in InP heterojunction bipolar transistor (HBT) technology by RSC operating at 150 GHz.
Finally, although the discussions above have highlighted the various IC technologies with which the Mayo team has worked in the recent past, much of the time we employ these technologies to create specific functionality required by our sponsors. The figure below illustrates the layout of an IC specifically designed by the Mayo team as an implementation of a direct digital synthesizer (DDS); this particular DDS implementation relies on a new algorithm, developed at Mayo, which greatly simplifies the design and decreases the power dissipation of a DDS function, with only a small loss in DDS generality. The IC was fabricated in IBM’s 8HP SiGe BiCMOS technology and tested in our laboratory.
Mayo designed "Cardinal" direct digital synthesizer with quadrature wideband chirp outputs, programmable starting phase, optional return to zero outputs, and digitally trimmable analog multipliers.
