With the required circuit and packaging models in-hand, the SPPDG can perform a wide range of analyses using a variety of tools, the most common of which is a signal integrity simulation of critical interconnect paths. Using custom scripts and tools, as well as common simulation engines, simple to complex input waveforms can be simulated and eye diagrams can be automatically generated for complex systems, which can then be used to aid in the proper design of the interconnect, input/output buffers, amplifiers, etc.
Example circuit simulation of 2.5 Gbps serial data stream between two components with variable board line length.
In addition, manufacturing tolerances can be taken into account with Monte-Carlo simulations to ensure proper operation under a wide variety of conditions. It is common to employ Monte Carlo techniques to model "best case" and "worst case" and corner conditions for the integrated circuits, but, as this example shows, it is also necessary to construct board level and system level interconnect models to accurately characterize signal behavior in the context of fabrication process variations in controlled impedance interconnect.
Example Monte-Carlo simulation showing variability in waveforms caused by variations in manufacturing tolerances.
For circuits with significant switching noise issues, the power and ground delivery system, along with decoupling capitance and associated parasitics, must also be modeled to determine their effects on signal integrity.
Block diagram of simultaneous switching noise (SSN) model of an integrated circuit on a multichip module includes package parasitics, on-chip and off-chip decoupling capacitance, and models for the MCM power planes.
In most instances, the complexity of the analyzed system falls well within the capability of the available simulation tools. Nonetheless, over the years there have been many instances in which the system being analyzed has been far too complex to be effectively simulated. One common example of an effect that for many years fell outside the effective capability of commercially available simulation tools was the analysis of noise on ground and power planes in mixed signal systems, where it is quite common to have dozens-to-hundreds of components attached to the ground and power planes. Mayo developed a number of new algorithms to predict the same noise surfaces through simulation tools. Within the past several years, commercially available simulation tools such as Apache Redhawk-SDL have become available that can analyze dynamically the quality of power and ground distribution on very large integrated circuits. Although such tools are computation-intensive and must be run on our largest compute server platforms, and although there is a significant learning curve for these tools to be exploited fully, their ability to reveal power distribution anomalies in large digital integrated circuits has proven to be helpful in assuring first-pass success on these expensive components. The figure below depicts before-and-after views of a 223 million transistor bulk CMOS application-specific integrated circuit (ASIC), illustrating significant areas of supply voltage "droop" in the central region of the leftmost, "before" image, and the rerun simulation, illustrating significant improvement, after decoupling capacitance was added to the chip and the DC supply metalization was improved.
Comparison of on-chip dynamic voltage supplyVdd droop across 223 million transistor ASIC showing initial design and final design with added decoupling capacitance and enhanced Vdd power grid.
